1. Field of the Invention
The present invention relates to a NOR nonvolatile semiconductor storage device having a source electrode of a local interconnection type and a method of manufacturing the same. In particular, it is applied to formation of a source region and a drain region that have a self-aligned contact structure.
2. Background Art
Improvement of the performance of semiconductor integrated circuits has led to development of microprocessors and bulk semiconductor memories and thus has made a contribution to advancement of the information society.
A nonvolatile semiconductor memory can be electrically written or erased and maintain data even after the power supply is turned off. The nonvolatile semiconductor memory, which has increased its storage capacity, is now dominating the conventional magnetic recording media, such as hard disks, in the storage media market.
Downsizing of semiconductor integrated circuits has made a great contribution to such advancement of the technology. And the downsizing of semiconductor integrated circuits is based on the photolithography technique. The photolithography technique has recently achieved a resolution of the order of nanometers and is expected to achieve even finer resolutions.
The photolithography technique involves a scanner that projects a desired pattern of light onto a photoresist applied on a semiconductor wafer for exposure and an exposure mask having a fine pattern referred to as reticle. In the photolithography technique, patterning of a contact hole is particularly difficult.
A transistor, which is an essential component of an integrated semiconductor circuit, has fine diffusion layers referred to as drain region and source region. To form wiring, contacts have to be formed through the fine diffusion layers and a contact hole or a local interconnection groove formed in an interlayer insulating film.
In particular, the contact hole connected to the drain region has to be reliably formed on the fine diffusion layer without forming a short circuit to an adjacent bit.
In the following, a memory cell array of a NOR flash memory will be described in particular.
The memory cell array of the NOR flash memory is composed of memory cells “MC” arranged in a matrix. Bit lines “BL” extend in the column direction of the memory cell array, and word lines “WL” and source lines “LI” extend in the row direction of the memory cell array.
In the memory cell array, the memory cells “MC” in each column are connected in series with each other so that adjacent memory cells share a source region and a drain region. That is, adjacent memory cells “MC” are arranged to share a source region and a drain region. Each bit line “BL” forms a drain contact layer “DC” together with the drain regions of the memory cells “MC” in one column. Each word line “WL” extends in the row direction and forms a common connection for one row of memory cells “MC” together with the control gate electrodes of the memory cells “MC”.
Therefore, the memory cell array of the NOR flash memory has to have one drain contact layer “DC” for connection to the bit line “BL” for every two memory cells. To this end, drain contact layers “DC” are periodically arranged in the memory cell array.
The drain contact layer “DC” is formed between the word line “WL” and a device isolation region, and higher precision of the drain contact holes is needed as the memory cells become smaller. Thus, higher machining precision of the memory cell array is needed.
However, from the viewpoint of reducing the contact resistance, the opening of the contact holes is preferably as large as possible. To this end, it is essential that the contact holes have the largest allowable opening.
The contact hole actually formed depends on the capability of the scanner and the photoresist, the capability of the etching apparatus, and finally the implantability of the region.
On the other hand, the source line “LI” extends in the row direction and forms a common connection for one row of the memory cell array.
The source region differs from the drain region in the relationship with the adjacent bits in the row direction. More specifically, the drain region has to be isolated from the adjacent bits in the row direction. To the contrary, the source region has only to be connected to the ground potential, and therefore, there is no problem if the source region is connected to the adjacent source region in the row direction.
Thus, the ground potential is supplied from the source wiring in the upper layer through a via that relays the source potential every several tens or several hundreds of bits.
The structure of the source region of the NOR memory cell is generally classified as the local interconnection (LI) type that obtains the ground potential from the source wiring in the upper layer through local interconnection wiring or the self-aligned source (SAS) type that obtains the ground potential via the adjacent cells through the diffusion layer (see National Publication of International Patent Application No. 2002-508589, for example).
For both the structures described above, the distance between the gate electrode and the drain contact layer has to be enough to achieve a required breakdown voltage and accommodate the misalignment of the lithography apparatus.
In the case of the LI type, in addition, the distance between the gate electrode and the source local interconnection wiring also has to be enough to achieve the required breakdown voltage and accommodate the misalignment.
On the other hand, the memory cell of the SAS type does not need consideration of the source side and can be downsized accordingly.
The most effective way of reducing the total area of a chip is to reduce the size of the memory cell array. However, reducing the size of each memory cell is not always the best way.
For example, supposing that the LI-type memory cell and the SAS-type memory cell are manufactured by the same manufacturing apparatus, the size of the memory cell itself is smaller for the SAS type than the LI type. However, the SAS type is supplied with the source potential at the diffusion layer having a high electrical resistance and therefore requires frequent supplies of the ground potential.
On the other hand, for the LI-type cell, the ground potential of the metal wiring layer in the upper layer can be supplied to the source diffusion layer via tungsten or the like. Therefore, the LI-type cell requires a smaller number of supply points than the SAS type.
Furthermore, for source potential supply of the SAS type, the word line has to be curved to prevent electrical contact between the source contact and the word line. Then the pitch of the word line increases.
To the contrary, for source potential supply of the LI type, the source potential can be supplied in a two-dimensional manner, so that the area required for supply of the source potential can be reduced compared with the SAS type.
Therefore, for a large-scale memory cell array, the LI type can be smaller than the SAS type, although individual memory cells of the LI type are larger than those of the SAS type.